The present invention relates to a semiconductor integrated circuit apparatus, and more particularly to a technology for measuring and managing a physical amount that exerts an influence upon an operation of a semiconductor integrated circuit.
Generally, when the semiconductor integrated circuit apparatus (high-speed LSI) packed on a system failed, the system having it mounted comes not to operate normally in some cases, and the system down occurs in some cases, which causes the operation of system to stop. For this, various inspections are made to improve performance and quality of the high-speed LSI so that the high-speed LSI under operation does not fail.
As one of general inspection methods, there is a method of using a BIST (Built-In Self Test) for inspection (for example, a patent document 1). In the patent document 1, a technology was disclosed of providing a BIST function in a send unit, a receive unit, a control unit, and a central logical unit to inspect a signal interconnection. Further, a technology of using the BIST for inspection to manage an inspection result was also proposed (for example, a patent document 2).
Also, there is a method of making an inspection by specifying factors that cause performance of the semiconductor integrated circuit to decline.
For example, in designing the high-speed LSI of late years, power source noise and clock jitter are listed as a main factor of hindering performance improvement. So as to measure such power source noise and clock jitter, an inspection is made by making a probing measurement from the outside of the LSI to evaluate a power source noise waveform and a peak value of the clock jitter.
Further, as a factor of hindering the performance improvement other than the foregoing, a malfunction in a step of assembling a semiconductor apparatus is listed. So as to prevent a decline in performance and quality that stems from the malfunction in a step of assembling the semiconductor apparatus, there is a method of inspecting the semiconductor integrated circuit to analyze the step in which the cause of the performance decline originates, and of stopping a manufacturing apparatus of its step, or adjusting the manufacturing apparatus responding to a necessity (for example, a patent document 3).
Also, as a malfunction of the high-speed LSI, degradation that comes out as an operating hour elapses is listed. A technology for integrating the operating hour in order to recognize a degradation situation etc. was also proposed (for example, a patent document 4).
Yet further, a technology of, by monitoring power consumption, making management so that no malfunction occurred was also proposed (for example, a patent document 5).
[PATENT DOCUMENT 1] Laid-Open of PCT translation No. 2003-529145
[PATENT DOCUMENT 2] JP-P1999-31399A
[PATENT DOCUMENT 3] JP-P1996-195406A
[PATENT DOCUMENT 4] JP-P1993-326845A
[PATENT DOCUMENT 5] JP-P2003-7838A
The above-mentioned prior arts, however, accompanied the following problems.
In a case of using the BIST for inspection like the patent document 1 or the patent document 2, there was a case where the malfunction occurred beyond its prediction in the actual operation because test data was prepared responding to its use situation for inspection. Also, it was difficult to predict the noise or the jitter in designing.
Further, in a case of using the BIST for inspection, there was no chance that the semiconductor integrated circuit other than the semiconductor integrated circuit that was an object of measurement operated actually (a stop state etc.), so when it was caused to operate actually, it received an influence from the other semiconductor integrated circuit apparatus, and failed in some cases.
Also, the factor that causes the performance of the semiconductor integrated circuit to decline is not only one factor, and there was also a case where various factors were piled upon, and the performance declined. For this, in a case where the various factors were piled up, and the performance declined, its factors were impossible to analyze and remove because the inspection item (measurement content) was limited to a specified one in the foregoing prior art.
Further, in a case of measuring the noise or the jitter, the noise or the jitter on the LSI was impossible to measure in the high-speed LSI. Its reason is that a high-speed signal on the LSI is impossible to output to the outside of the LSI because a band degrades due to a pad or a pin of a package. Also, even though the probing measurement was employed, it was difficult to make a probing measurement of the just neighborhood of a point that is required to measure in the package of numerously employed flip-chips in the high-speed LSI.
Further, the problem lay in that it was difficult to predict the noise or the jitter that exerted an influence upon the operation of the semiconductor integrated circuit in designing, and in addition hereto, it was very difficult to reduce the noise or the jitter after manufacturing the LSI. With the noise, in a case where it was found that the power source noise was excessive after manufacturing the LSI, the problem existed that adding the LSI having an on-chip decoupling capacity that was a countermeasure to the power source noise gave rise to high cost and delay in development. With the jitter, as a parameter that exerts an influence upon the jitter of a phase-locked loop (hereinafter, referred to as a PLL) for generating a clock signal, there are a resistance value or a capacity value of a loop filter configuring the PLL, a gain of a voltage control oscillator, a current value of a power source of a charge pump circuit, and a frequency dividing number of a divider. However, the parameter was impossible to decide clearly because the actual jitter value was unknown, whereby it was very difficult to design the PLL having low jitter.
Further, it was difficult to find a countermeasure for lowering the noise and the jitter that were main factors exerting an influence upon the operation of the semiconductor integrated circuit. For example, as a rule, the cause of the jitter originates in the power source noise, and a strong correlation exists between the jitter and the power source noise. Accordingly, so as to reduce the jitter, the power source noise has to be reduced. So as to reduce the power source noise, a power source system of anyone of a board, the package, and the LSI has to be modified. As shown in FIG. 46, the low-frequency power source noise is decided by the power source system of the board, the intermediate-frequency power source noise is decided by the power source system of the package, and the high-frequency power source noise is decided by the power source system of the LSI. However, in the conventional evaluation of the peak value of the jitter and the waveform of the power source noise, it was impossible to clearly know which portion of the power source system had to be corrected, so there was no choice but take a countermeasure on a trial and error basis, which was poor in efficiency.